high - accuracy eprom programmable pll die for crystal oscillators cy2037 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07354 rev. *d revised february 26, 2007 features ? eprom-programmable die for in-package programming of crystal oscillators ? high resolution pll with 12-bit multiplier and 10-bit divider ? eprom-programmable capacitor tuning array with shadow register ? twice programmable die (cy2037a, cy2037b [1] and cy2037-2). ? simple 4-wire programming interface ? on-chip oscillator runs from 10?30 mhz fundamental tuned crystal ? eprom-selectable ttl or cmos duty cycle levels ? operating frequency ? 1?133 mhz at 5v ? 1?100 mhz at 3.3v ? 1?66.6 mhz at 2.7v ? sixteen selectable post-divid e options, using either pll or reference oscillator output ? programmable power down (pd#) or oe pin (cy2037a, cy2037b, and cy2037-2) ? frequency select (cy2037-3) ? programmable asynchronous or synchronous oe and power down (pd#) modes (cy2037a, cy2037b and cy2037-2) ? low jitter outputs typically ? < 100 ps (pk-pk) at 5v and f>33 mhz ? < 125 ps (pk-pk) at 3.3v and f>33 mhz ? 3.3v or 5v operation ? small die ? controlled rise and fall times and output slew rate benefits ? enables quick turnaround of custom oscillators ? lowers inventory costs thro ugh stocking of blank parts ? enables synthesis of highly accurate and stable output clock frequencies with zero or low ppm ? enables fine-tuning of output clock frequency by adjusting c load of the crystal ? enables reprogramming of programmed part, to correct errors, and control excess inventory ? enables programming of output frequency after packaging ? lowers cost of oscillator as pll can be programmed to a high frequency using a low-frequency, low-cost crystal ? duty cycle centered at 1.4v or v dd /2 ? provides flexibility to service most ttl or cmos applica- tions ? services most pc, networking, and consumer applications ? provides flexibility in out put configurations and testing ? enables low-power operation or output enable function ? enables two frequency options fo r meeting different industry standards, i.e., pal/ntsc ? provides flexibility for system applications, through selectable instantaneous or synchronous change in outputs ? suitable for most pc, consumer, and networking applica- tions ? lowers inventory cost as same die services both applica- tions ? enables encapsulation in small-size, surface mount packages ? has lower emi than oscillators note 1. the cy2037a and cy2037b are identical. however, the cy2037b is recommended for all new designs table 1. device functionalit y: output frequencies parameter description condition min. max. unit fo output frequency v dd = 4.5v?5.5v 1 133 mhz v dd = 3.0v?3.6v 1 100 mhz v dd = 2.7v?3.0v 1 66 mhz [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 2 of 10 x g pd#/oe x d configuration crystal clkout / 1, 2, 4, 8, 16, 32, 64, 128 oscillator or fs mux high accuracy pll eprom logic block diagram x y vdd vdd xd xg pd#/oe or fs n/c clkout vss vss horizontal scribe xx n/c xr device name vertical scribe note: active die size: x = 55.9 mils / 1420.1 m bond pad opening: 85 m x 85 m pad pitch: 125 m x 125 m (pad center to pad center) scribe: x (horizontal)= 2.6 mils / 65.6 m y (vertical)= 3.0 mils / 76.9 m die pad description note 2. for customers not bonding the x d or x g pad to external pins, an alternative bonding option would be shorting the xx pad to the x d pad die pad summary name die pad description x coordinate ( m) y coordinate ( m) v dd 1,2 voltage supply 124.7 855.6 , 731 v ss 8,9 ground 1291.35 99.6 , 225.2 x d 4 crystal connection. 124.7 481.8 x x 3 no connect [2] 124.7 606.4 x g 6 crystal connection. 124.7 232.6 pd#/oe or fs 7 cy2037a, cy2037b, and cy2037-2?eprom programmable power down or output enable pad. cy2037-3?frequency select. serves as v pp in programming mode for all devices. 124.7 108 clkout 11 clock output. also serves as three-state input during programming. 1282.45 901.8 n/c 5,10 no connect. (do not bond to these pads) 124.7,1282.45 357.2, 769.4 [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 3 of 10 functional description the cy2037 is an eprom programmable, high accuracy, pll-based die designed for the crystal oscillator market. the die attaches directly to a low-cost 10?30 mhz crystal and can be packaged into 4-pin through-hole or surface mount packages. the oscillator devic es can be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. this enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. the cy2037 contains an on-chip oscillator and a unique oscil- lator tuning circuit for fine-tuning of the output frequency. the crystal c load can be selectively adjusted by programming a set of seven eprom bits. this feature can be used to compensate for crystal variations or to obtain a more accurate synthesized frequency. the cy2037 uses eprom programming with a simple 2-wire, 4-pin interface that includes v ss and v dd . clock outputs can be generated up to 133 mhz at 5v or up to 100 mhz at 3.3v. the entire configuration can be reprogrammed one time, allowing programmed inventory to be altered or reused. the cy2037 pll die has been designed for very high resolution. it has a 12-bit feedback counter multiplier and a 10-bit reference counter divider. this enables the synthesis of highly accurate and stable output clock frequencies with zero or low ppm error. the clock can be further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64, and 128. the divider input can be selected as either the pll or crystal oscil- lator output providing a total of sixteen separate output options. for further flexibility, the ouput is selectable between ttl and cmos duty cycle levels. the cy2037a, cy2037b and cy2037-2 also contain flexible power management controls. these parts include both power down (pd#) and oe features wit h integrated pull-up resistors. the pd# and oe modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. when pd# or oe modes are enabled, clkout is pulled low by a weak pull down. the weak pull down is easily overdriven by an other active clkout for appli- cations that require multiple clkouts on a single signal path. controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the cy2037 to have low jitter and accurate outputs, making it suitable for most pc, networking, and consumer applications. on the other hand, the cy2037-3 contains a frequency select function in place of the power down and output enable modes. for example, consumer products often require frequency compatibility with different electrical standards around the world. with this frequency select feature, a product that incor- porates the cy2037-3 could be compatible with both ntsc for north american and pal for europe simply by changing the fs line. the twice programmable feature is also absent in the cy2037-3, because the second eprom row is now being used for the alternate frequency. eprom configuration block ta b l e 2 summarizes the features that are configurable by eprom. please refer to the ?7c8038x/7c8034x programming specification? for further details. the specifi- cation can be obtained from your cypress factory represen- tative. . pll output frequency the cy2037 contains a high-resolution pll with 12-bit multi- plier and 10-bit divider.the output frequency of the pll is determined by the following formula: where p is the feedback counter value and q is the reference counter value. p and q are eprom programmable values. power management features (except cy2037-3) the cy2037 contains eprom-programmable pd# and oe functions. if powerdown is select ed, all active circuitry on the chip is shut down when the control pin goes low. the oscillator and pll circuits must re-lock when the part leaves powerdown mode. if output enable mode is selected, the output is tri-stated and weakly pulled low when the control pin goes low. in this mode the oscillator and pll circuits continue to operate, allowing a rapid return to normal operation when the control input is deasserted. in addition, the pd# and oe modes can be programmed to occur synchronously or asynchronously with respect to the output signal. when the asynchronous setting is used, the power down or output disable occurs immediately (allowing for logic delays) regardless of po sition in the clock cycle. however, when the synchronous setting is used, the part waits for a falling edge at the output before the power down or output enable signal is initiated, th us preventing output glitches. in either asynchronous or synchro nous setting, the output is always enabled synchronously by waiting for the next falling edge of the output. table 2. eprom adjustable features adjust frequency feedback counter value (p) reference counter value (q) output divider selection oscillator tuning (load capacitance values) duty cycle levels (ttl or cmos) power management mode (oe or pd#) power management timing (synchronous or asynchronous) f pll 2p5 + () ? q2 + () --------------------------- f ref ? = [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 4 of 10 crystal oscillator tuning circuit the cy2037 contains a unique tuning circuit to fine-tune the output frequency of the device. the tuning circuit consists of an array of eleven load capacitors on both sides of the oscil- lator drive inverter. the capacitor load values are eprom programmable and can be increased in small increments. as the capacitor load is increased the circuit is fine-tuned to a lower frequency. the capacitor load values vary from 0.17 pf to 8 pf for a 100:1 total control ratio. the tuning increments are shown in the table below. please refer to the ?7c8038x/7c8034x programming specification? for further details. figure 1. crystal oscillator tuning circuit cd = eprom bit t = transistor c = load capacitor cd6 c6 cd5 c5 cd4 c4 cd3 c3 cd2 c2 cd1 c1 cd0 c0 cd3 c7 cd4 c8 cd5 c9 cd6 c10 external crystal cgo cdo rf table 3. crystal oscillator parameter table. parameter description min. typ. max. unit r f feedback resistor, v dd = 4.5?5.5v feedback resistor, v dd = 2.7?3.6v 0.5 1.0 2 4 3.5 9.0 m m capacitors have 20% tolerance c g gate capacitor 13 pf c d drain capacitor 9 pf c 0 series cap 0.27 pf c 1 series cap 0.52 pf c 2 series cap 1.00 pf c 3 series cap 0.7 pf c 4 series cap 1.4 pf c 5 series cap 2.6 pf c 6 series cap 5.0 pf c 7 series cap 0.45 pf c 8 series cap 0.85 pf c 9 series cap 1.7 pf c 10 series cap 3.3 pf [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 5 of 10 difference between cy2037a/cy2037b and cy2037-2 the cy2037a/cy2037b contains a shadow register in addition to the eprom register. the shadow register is an exact copy of the eprom register and is the default register when the valid bit is not set. it is useful when the prototype or production environment calls for measuring and adjusting the clkout frequency numerous times. multiple adjustments can be performed with the shadow register. once the desired frequency is achieved the eprom register is permanently programmed. some production flows do not require the use of the shadow register. if this is the case, t hen the cy2037-2 is the device of choice. the cy2037-2 has a disabled shadow register. the cy2037-3 contains the shadow register. frequency select feature of cy2037-3 the cy2037-3 contains a frequency select function in place of the powerdown and the output enable functions. with the frequency select featur e, customers can switch two different frequencies that are configured in the two eprom rows. the definition of the frequency select pin (fs) is ta b l e 4 . . table 4. frequency select pin decoding for cy2037-3 fs pin output frequency 0 from eprom row 0 configuration 1 from eprom row 1 configuration [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 6 of 10 absolute maximum ratings [3] supply voltage ..................................................?0.5 to +7.0v input voltage .............................................. ?0.5v to v dd +0.5 storage temperature (non-condensing).... 55c to +150c junction temperature ................................. ?40c to +100c static discharge voltage......... .............. .............. ...... > 2000v (per mil-std-883, method 3015) operating conditions parameter descrip tion min. max. unit v dd supply voltage (3.3v) supply voltage (5.0v) 2.7 4.5 3.6 5.5 v v t aj [4] operating temperature, junction ?10 +100 c c ttl max. capacitive load on outputs for ttl levels v dd = 4.5?5.5v, output frequency = 1?40 mhz v dd = 4.5?5.5v, output frequency = 40?133 mhz 50 25 pf pf c cmos max. capacitive load on outputs for cmos levels v dd = 4.5?5.5v, output frequency = 1?66.6mhz v dd = 4.5?5.5v, output frequency = 66.6?133mhz v dd = 3.0?3.6v, output frequency = 1?40 mhz v dd = 3.0?3.6v, output frequency = 40?100 mhz v dd = 2.7?3.0v, output frequency = 1?66 mhz 50 25 30 15 15 pf pf pf pf pf x ref reference frequency, input crystal. fundamental tuned crystals only. 10 30 mhz t pu power-up time for all vdds to reach mi nimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics over the operating range (part was characteri zed in a 20-pin soic package with external crystal, electrical characteristics may change with other package types.) parameter description test conditions min. typ. max. unit v il low-level input voltage v dd = 4.5v?5.5v v dd = 2.7v?3.6v 0.8 0.2v dd v v v ih high-level input voltage v dd = 4.5v?5.5v v dd = 2.7v?3.6v 2.0 0.7v dd v v v ol low-level output voltage v dd = 4.5v?5.5v, i ol = 16 ma v dd = 2.7v?3.6v, i ol = 8 ma 0.4 0.4 v v v ohcmos high-level output voltage, cmos levels v dd = 4.5v?5.5v, i oh = ?16 ma v dd = 2.7v?3.6v, i oh = ?8 ma v dd ? 0.4 v dd ? 0.4 v v v ohttl high-level output voltage, ttl levels v dd = 4.5v?5.5v, i oh = ?8 ma 2.4 v i il input low current v in = 0v 10 a i ih input high current v in = v dd 5 a i dd power supply current, unloaded v dd = 4.5v?5.5v, output frequency <= 133mhz v dd = 2.7v?3.6v, output frequency <= 100 mhz 45 25 ma ma i dds [5] stand-by current v dd = 2.7v?3.6v 10 50 a r up input pull-up resistor v dd = 4.5v?5.5v, v in = 0v v dd = 4.5v?5.5v, v in = 0.7v dd 1.1 50 3.0 100 8.0 200 m k i oe_clkout clkout pull-down current v dd = 5.0 20 a notes 3. stresses greater than listed may impair the life of the device. 4. this product is sold in die form so operating conditi ons are specified for the die, or junction temperature 5. if external reference is used, it is required to stop the reference (set reference to low) during power down [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 7 of 10 output clock switching characteristics over the operating range [6] parameter description test conditions min. typ. max. unit t 1w output duty cycle at 1.4v, v dd = 4.5?5.5v t 1w = t 1a t 1b 1?40 mhz, c l <=50 pf 40?66 mhz, c l <=15 pf 66?125 mhz, c l <=25 pf 125?133 mhz, c l <=15 pf 45 45 40 40 55 55 60 60 % % % % t 1x output duty cycle at v dd /2, v dd = 4.5?5.5v t 1x = t 1a t 1b 1?66.6 mhz, c l <=25 pf 66.6?125 mhz, c l <=25 pf 125?133 mhz, c l <=15 pf 45 40 40 55 60 60 % % % t 1y output duty cycle at v dd /2, v dd = 3.0?3.6 t 1y = t 1a t 1b 1?40 mhz, c l <=30 pf 40?100 mhz, c l <=15 pf 45 40 55 60 % % t 1z output duty cycle at v dd /2, v dd = 2.7?3.0 t 1y = t 1a t 1b 1?40 mhz, c l <=15 pf 40?66.6 mhz, c l <=10 pf 40 40 60 60 % % t 2 output clock rise time between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 50 pf between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 25 pf between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 15 pf between 0.2v dd ?0.8v dd , v dd = 4.5v?5.5v, c l = 50 pf between 0.2v dd ?0.8v dd , v dd = 3.0v?3.6v, c l = 30 pf between 0.2v dd ?0.8v dd , v dd = 2.7v?3.6v, c l = 15 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 3 output clock fall time between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 50 pf between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 25 pf between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 15 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v-5.5v, c l = 50 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 30 pf between 0.2v dd ? 0.8v dd , v dd = 2.7v?3.6v, c l = 15 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 4 start-up time out of power d own pd# pin low to high [7] 12ms t 5a power down delay time (synchronous setting) pd# pin low to output low (t = period of output clk) t/2 t+10 ns t 5b power down delay time (asynchronous setting) pd# pin low to output low 10 15 ns t 6 power up time from power on [7] 12ms t 7a output disable time (synchronous setting) oe pin low to output hi-z (t = period of output clk) t/2 t+10 ns t 7b output disable time (asynchronous setting) oe pin low to output hi-z 10 15 ns t 8 output enable time (always synchronous enable) oe pin low to high (t = period of output clk) t1.5t+2 5 ns t 9 peak-to-peak period jitter v dd = 4.5v?5.5v, fo > 33 mhz, vco > 100 mhz v dd = 2.7v?3.6v, fo > 33 mhz, vco > 100 mhz v dd = 2.7v?5.5v, fo < 33 mhz 100 125 250 125 200 1% of f o ps ps ps notes 6. not all parameters measured in production testing. 7. oscillator start time cannot be guaranteed for all crystal type s. this specification is for operation with at cut crystals wi th esr < 70 ohms. [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 8 of 10 switching waveforms figure 2. duty cycle timing (t 1w, t 1x, t 1y , t 1z ) figure 3. output rise/fall time figure 4. power down timing (synchronous and asynchronous modes) figure 5. power-up timing t 1a t 1b output output t 2 v dd 0v t 3 clkout v dd t 4 1/f t 5a v il v ih power down 0v 1/f t 5b clkout t (synchronous [ 8] ) (asynchronous [ 9] ) clkout v dd t 6 1/f v dd ? 10% power up 0v min. 30 s max. 30 ms notes 8. in synchronous mode the power down or output tri-state is not initiated until the next falling edge of the output clock. 9. in asynchronous mode the power down or output tri-state occu rs within 25 ns regardless of pos ition in the ouput clock cycle. [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 9 of 10 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. ] ordering information [10] ordering code type wafer thickness operating range cy2037awaf [11] wafer 14 0.5 mils ?10 c to +100 c cy2037-2waf [11] wafer 14 0.5 mils ?10 c to +100 c CY2037-3WAF [11] wafer 14 0.5 mils ?10 c to +100 c cy2037bwaf wafer 14 0.5 mils ?10 c to +100 c cy2037b-11waf wafer 11 0.5 mils ?10 c to +100 c note 10. the only difference between the cy2037a/cy2037b and the cy2037-2 is that the cy2037-2 has the shadow register disabled. the cy2037-3 replaces the power-down options with a frequency select , and contains the shadow register. 11. the cy2037b is recommended for all new designs [+] feedback [+] feedback
cy2037 document #: 38-07354 rev. *d page 10 of 10 document history page document title: cy2037 high-accuracy eprom pr ogrammable pll die for crystal oscillators document number: 38-07354 rev. ecn no. issue date orig. of change description of change ** 112248 03/01/02 dsg change from spec number: 38-00679 to 38-07354 *a 121857 12/14/02 rbi power-up requirements added to operating conditions information *b 291092 see ecn rgl updated min. operating temperature, junction *c 522769 see ecn rgl added cy2037b information. updated absolute maximum junction temper- ature specificatio n. updated ordering information table. added die pad description and coordinates *d 804376 see ecn rgl minor change: to post on web [+] feedback [+] feedback
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